2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (ULIS)

April 3-5, 2017 - Athens, Greece

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Welcome!

A very warm welcome to the 3rd joined EUROSOI - ULIS 2017 Conference, here in Athens! This Conference aims at gathering together in an interactive forum all scientists and engineers working in the field of SOI technology and advanced nanoscale devices. One of the key objectives of the conference is to promote collaboration and partnership between different academia, research and industry players in the field. This year the joint EUROSOI-ULIS event will be hosted by the Institute of Nanoscience & Nanotechnology of NCSR “Demokritos” in Athens, Greece.

Call for Papers

The organizing committee invites scientists and engineers working in the above fields to actively participate by submitting high quality papers. Original 2-page abstracts with illustrations will be accepted for review in pdf format. The accepted abstracts will be published in a Proceedings book with an ISBN. A 4-page follow-up paper delivered before April 3, 2017 will be published in IEEE Xplore Digital Library. The authors of the best papers will be invited to submit a longer version for publication in a special issue of Solid-State Electronics. A best paper award will be attributed to the best paper by the SINANO institute.

Important Dates

Abstract Submission Deadline: January 20, 2017

Conference Dates: April 3-5, 2017

Early registration: February 10, 2017

Topics include, but are not limited to :
  • Advanced SOI materials and wafers. Physical mechanisms and innovative SOI-like devices.
  • New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V and high mobility materials on insulator; carbon nanotubes; graphene and other two-dimensional materials.
  • Properties of ultra-thin films and buried oxides, defects, interface quality. Thin gate dielectrics: high-k materials for switches and memory.
  • Nanometer scale devices: technology, characterization techniques and evaluation metrics for high performance, low power, low standby power, high frequency and memory applications.
  • Alternative transistor architectures including FDSOI, DGSOI, FinFET, MuGFET, vertical MOSFET, Nanowires, FeFET and Tunnel FET, MEMS/NEMS, Beyond-CMOS nanoelectronic devices.
  • New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain, nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc.
  • CMOS scaling perspectives; device/circuit level performance evaluation; switches and memory scaling. Three-dimensional integration of devices and circuits, heterogeneous integration.
  • Transport phenomena, compact modeling, device simulation, front- and back-end process simulation.
  • Advanced test structures and characterization techniques, parameter extraction, reliability and variability assessment techniques for new materials and novel devices.

News

Registration
Registration is now open. Click here to register
Abstract Submission
Abstract submission is now open. Submit your abstract here
Updated Deadline
The deadline for Abstract submission has been updated. The new deadline is 20th January 2017
1st Announcement
The 1st announcement of the EUROSOI-ULIS 2017 conference is released. Download here.

Sponsors